1. Field of the Invention
The present invention relates to power gating, and more particularly to a power network using a standard cell, a power gating cell and a semiconductor device using the power network.
2. Description of the Related Art
Recently, according to demand of market, electronic products have been developed for having a smaller size, a longer operating time, a bigger capacity and more functions. Particularly, low power and small size are essential to portable electronic products. Thus, semiconductor devices employed in the portable electronic products need to be low-powered and small-sized.
When a manufacturing process becomes elaborate and the power supply voltage is lowered, the size of the semiconductor devices can be reduced. In the semiconductor devices having a small size, however, a leakage current is increased in a standby mode and an operating speed is difficult to be increased in an active mode. To solve the above problems, multi threshold-voltage complementary metal oxide semiconductor (MTCMOS) has been proposed. A power consumption control method using the MTCMOS is referred to as a power gating. When a power network that adopts the power gating using the MTCMOS is used, the semiconductor devices can reduce the leakage current in a standby mode. FIG. 1 is a circuit diagram illustrating a conventional MTCMOS circuit.
Referring to FIG. 1, the conventional MTCMOS circuit includes a logic circuit 11, a header type power gating circuit 12, a footer type power gating circuit 13, a virtual power voltage rail 14, and a virtual ground voltage rail 15.
The logic circuit 11 is coupled to the virtual power voltage rail 14 and to the virtual ground voltage rail 15, respectively. The logic circuit 11 is provided with a virtual power voltage and a virtual ground voltage. The logic circuit 11 includes MOS transistors having a low threshold voltage so that the logic circuit 11 can operate at a fast speed in a low voltage condition (for example, in a condition of about 1V). In FIG. 1, the logic circuit 11 may include the MOS transistor or a logic gate that has a low threshold voltage. In general, a drain current increases when the threshold voltage of the MOS transistor is lowered. Thus, the logic circuit 11 that includes transistors having the low threshold voltage can be switched quickly. However, when the threshold voltage of the MOS transistor is lowered, the leakage current increases rapidly even in a low voltage condition of 1V. Thus, the logic circuit 11 requires a means for blocking the leakage current in a stand-by mode.
The header type power gating circuit 12 includes a first current switch that connects or disconnects a power voltage terminal VDD and the virtual power voltage rail 14 in response to a control signal SLEEP. The footer type power gating circuit 13 includes a second current switch that connects or disconnects a ground voltage terminal GND and the virtual ground voltage rail 15 in response to an inversion signal /SLEEP of the control signal SLEEP. The first current switch and the second current switch may be implemented with a transistor having a high threshold voltage. Because a leakage current is very small in the transistor having a high threshold voltage, the leakage current of the logic circuit 11 is almost completely prevented when the first current switch and the second current switch using the transistor having a high threshold voltage is disconnected. When a semiconductor device is designed by applying the power gating method, a power consumption of the semiconductor device in a standby mode may be reduced.
The first current switch and the second current switch preferably do not affect the operation of the logic circuit 11. Because a current of the logic circuit 11 flows through the first current switch and the second current switch, the first current switch and the second current switch require a large current capacity. Accordingly an occupation area of the first current switch and the second current switch is very large.
The semiconductor device may have function cells that perform various functions, respectively. A particular function cell such as an output maintenance circuit that is always operated may not need the power gating method. In addition, it may be undesirable to apply the power gating method to all function cells since the MTCMOS occupies a large area. Accordingly the power gating method may be selectively applied to the function cell having a great need to reduce the power consumption in a standby mode so as to simultaneously satisfy a small size and a low power consumption. In other words, the particular function cell may have a general structure without adopting the power gating method whereas the function cell having the standby mode may have a structure with adopting the power gating method.
FIG. 2 is a diagram illustrating a standard power gating cell according to a conventional power gating method.
Referring to FIG. 2, the standard power gating cell has a structure in which a header type power gating circuit field is added to a general standard cell. The standard power gating cell includes an operating circuit field 21 that is coupled between a virtual power voltage rail 24 and a ground voltage rail 25, and a power gating circuit field 22 that is coupled between a power voltage rail 23 and the virtual power voltage rail 24.
A semiconductor device can be designed such that the standard power gating cells replace the general standard cells. In such conventional designs, however, the general standard cell and the standard power gating cell have to be included each process that requires power gating, thereby increasing workload and complexity of the conventional design processes. On the other hand, a semiconductor device can be designed such that the power gating method is adopted without changing a design of the general standard cell. For example, one independent power gating cell including the power gating circuit can be used with the general standard cell, but a following problem is accompanied. A source and a body of transistor elements in the general standard cell are connected to a virtual voltage rail, and a body of a current switch in the power gating circuit has to be electrically disconnected to the source and the body of transistor elements in the general standard cell. Otherwise, a leakage current through the body of the current switch and thus a power gating effect is reduced. Therefore the current switch has to be sufficiently separated from the general standard cell and a size of the current switch and a separation field need to be increased according as a current through the general standard cell connected to the current switch is increased. It is difficult to change a design of the power gating cell whenever the size of the current switch is changed. Therefore, a design of the power gating cell capable of being applied to the general standard cell is required.